Traditional computers are grossly inefficient in terms of power and speed when running certain classes of interesting algorithms, such as massively interconnected neural networks. In this talk, I will describe IBM’s recent chip architecture—called TrueNorth—that is a flexible, efficient, and scalable platform for running large-scale spiking neural networks. TrueNorth’s key design choice is to use an on-chip network of lightweight cores (64-by-64 array), where each core operates in parallel and co-localizes computation (neurons) and memory (state and connections) to minimize data movement. With 5.4 billion transistors in a 28nm technology, TrueNorth has one million programmable neurons and 256 million configurable synapses, and consumes less than 100mW while running at real-time.
I will also describe our recent work to create a software ecosystem built on top of the TrueNorth hardware, which includes a functional simulator, programming language, and machine learning tools for training networks. This ecosystem has been successfully used by our team to develop a complex vision task (multi-object detection and classification) that achieves state-of-the art performance on the NeoVision tower dataset.
Finally, I will talk about our effort to scale up to larger networks by tiling chips in two dimensions, which is natively supported by TrueNorth's inter-chip communication interface. Specifically, I will present results from our latest 4-by-4 chip system that has 16 million neurons and 4 billion synapses.
Paul Merolla received his PhD from the University of Pennsylvania in Bioengineering (2006) and a BS from the University of Virginia in Electrical Engineering (2000). He was a postdoctoral scholar in Stanford's Brains in Silicon lab (2006 - 2010). He has been a research scientist in IBM's Brain-Inspired Computing group since 2010.
Hosted by Aurel A. Lazar.